Led having a low defect n-type layer that has grown on a silicon substrate

ABSTRACT

A vertical GaN-based blue LED has an n-type GaN layer that was grown directly on Low Resistance Layer (LRL) that in turn was grown over a silicon substrate. In one example, the LRL is a low sheet resistance GaN/AlGaN superlattice having periods that are less than 300 nm thick. Growing the n-type GaN layer on the superlattice reduces lattice defect density in the n-type layer. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate is then removed. Electrodes are added and the structure is singulated to form finished LED devices. In some examples, some or all of the LRL remains in the completed LED device such that the LRL also serves a current spreading function. In other examples, the LRL is entirely removed so that no portion of the LRL is present in the completed LED device.

TECHNICAL FIELD

The present disclosure relates generally to GaN-based blue LEDs manufactured on silicon substrates and related methods and structures.

BACKGROUND INFORMATION

A Light Emitting Diode (LED) is a solid state device that converts electrical energy to light. Light is emitted from an active layer of semiconductor materials sandwiched between oppositely doped layers when a voltage is applied across the doped layers. There are many different LED device structures that are made of different materials and have different structures and perform in different ways. Some emit laser light, and others generate non-monochromatic and non-coherent light. Some are optimized for performance in particular applications. Some are high power devices and others are not. Some emit light as infrared radiation, whereas others emit visible light of various colors, and still others emit ultraviolet light. Some are expensive to manufacture, whereas others are less expensive. For commercial general lighting applications, a blue LED structure is often used. Such a blue LED having a Multiple Quantum Well (MQW) active layer involving Indium-gallium-nitride may, for example, emit non-monochromatic and non-coherent light having a wavelength in a range from 440 nanometers to 490 nanometers. A phosphor coating is then typically provided that absorbs some of the emitted blue light. The phosphor in turn fluoresces to emit light of other wavelengths so that the light the overall LED device emits has a wider range of wavelengths. The overall LED device that emits the wider range of wavelengths is often referred to as a “white” LED.

Although gallium-nitride substrate wafers are available, they are very expensive. The epitaxial layers of commercial blue LEDs are therefore typically grown on wafers of other types of substrates such as, for example, sapphire wafers. These other substrates are, however, still undesirably expensive. Common integrated circuits of the type employed in personal computers are generally fabricated on silicon substrates. As a result of the high volumes of silicon substrates produced for the computer industry, silicon substrates are relatively inexpensive as compared to sapphire substrates. Moreover, second hand semiconductor processing equipment for processing silicon substrate wafers is often available at low prices due to the fact that integrated circuit fabrication companies frequently upgrade their fabrication facilities in order to keep up with advances in integrated circuit manufacturing technology. It therefore would be desirable from a cost point of view to be able to fabricate GaN-based LEDs on relatively inexpensive silicon substrate wafers and to use the available second hand semiconductor processing equipment for processing such silicon wafers, but there are many problems with growing high quality GaN epitaxial layers on silicon substrates.

Many of the problems associated with growing high quality GaN epitaxial layers on silicon substrates derive from the fact that the lattice constant of silicon is substantially different from the lattice constant of GaN. When GaN is epitaxially grown on a silicon substrate, the epitaxial material being grown may exhibit an undesirably high density of lattice defects. If the GaN layer is grown to be thick enough, then stress within the GaN layer may result in a type of cracking in the latter grown portions of the GaN material. Moreover, silicon and GaN have different coefficients of thermal expansion. If the temperature of a structure involving GaN disposed on a silicon substrate is increased, for example, then the silicon material portion of the structure will expand at a different rate from the rate at which the GaN material expands. These different rates of thermal expansive give rise to stress between the various layers of the LED device. This stress may cause cracking and other problems. Furthermore, it is difficult to grow GaN on silicon substrate because GaN is a compound material and Si is an elemental material. The transition from nonpolar to polar structure, combined with the substantial lattice mismatch, generates defects. For these and other reasons, the epitaxial LED structure portions of most commercially-available white LED devices are not grown on silicon substrates. Improved processes and structures for fabricating blue LEDs on silicon substrates are sought.

The manufacture of blue LEDs grown on silicon substrates also typically involves wafer bonding. In one prior art process, an epitaxial blue LED structure is grown on a non-GaN substrate to form a device wafer structure. A layer of silver is formed on the epitaxial LED structure to function as a mirror. A barrier metal layer involving multiple periods of platinum and titanium-tungsten is then disposed on the silver mirror. The platinum layer in each period is a thin 60 nm layer. The titanium/tungsten layer in each period is about 10 nm thick and involves about approximately ninety percent tungsten. Five or more such periods are provided. Once the device wafer structure has been formed in this way, a carrier wafer structure is wafer bonded to the device wafer structure. The original non-GaN substrate of the device wafer structure is then removed and the resulting wafer bonded structure is singulated to form LED devices. In this prior art process, a layer of bonding metal is used to wafer bond the carrier wafer structure to the device wafer structure. This bonding metal layer involves a gold/tin sublayer. When the gold/tin sublayer is melted during wafer bonding, tin from this gold/tin sublayer does not penetrate into the silver layer due to the thickness of the multi-period barrier metal layer and due to a short high temperature cycle being used to melt the bonding metal. This prior art process is recognized to work well.

SUMMARY

In a first novel aspect, a white LED assembly involves a blue LED device. The blue LED device is manufactured by epitaxially growing a Low Resistance Layer (LRL) over a silicon substrate. In one example, a buffer layer is grown directly on the silicon wafer substrate, and then a template layer of undoped gallium-nitride is grown directly on the buffer layer, and then the LRL is grown directly on the template layer.

In one example, the LRL is a superlattice structure involving multiple periods, where each period is thin (less than 300 nm thick) and involves a relatively thick gallium-nitride sublayer (for example, 100 nm thick) and a relatively thin undoped aluminum-gallium-nitride sublayer (for example, 25 nm thick). The bottom sublayer of the LRL is a sublayer of GaN. The top sublayer of the LRL is also a sublayer of GaN. There are four undoped aluminum-gallium-nitride sublayers in the LRL.

The blue LED device involves an indium-containing light-emitting active layer sandwiched between two oppositely doped layers. This structure of an active layer sandwiched between two oppositely doped layers is referred to here as a “PAN structure”. The n-type layer of the PAN structure is grown directly on the upper surface of the LRL so that the n-type layer is disposed directly on a GaN sublayer of the LRL. The n-type layer may involve periods of gallium-nitride and aluminum-gallium-nitride as well, but the gallium-nitride sublayers of the n-type layer are substantially thicker than are the gallium-nitride sublayers of the LRL. In addition, the aluminum-gallium-nitride sublayers of the n-type layer are substantially thinner than are the aluminum-gallium-nitride sublayers of the LRL. The aluminum-gallium-nitride sublayers of the n-type layer are silicon doped to have a silicon concentration of more than 1×10¹⁸ atoms/cm³, whereas the aluminum-gallium-nitride sublayers of the LRL layer are undoped and have a silicon concentration of less than 1×10¹⁸ atoms/cm³.

In subsequent processing, the face side of the silicon device wafer structure is wafer bonded to a carrier wafer structure involving a conductive carrier. The conductive carrier may, for example, be a monocrystalline silicon wafer that is doped to be conductive. After this wafer bonding, the original silicon wafer substrate is removed by chemical mechanical polishing and/or by other suitable methods.

In a first specific example, the original silicon wafer substrate, the buffer layer and the template layer are removed but at least a portion of the LRL layer is left. After the removal step, the exposed surface of the LRL that remains is a sublayer of gallium-nitride. Electrodes are added and the wafer bonded structure is singulated into individual blue LED devices. Within each blue LED device, the n-type layer of the PAN structure is in direct contact with at least a portion of the LRL layer. The LRL layer has a sheet resistance at the LRL/n-type layer interface that is lower than the sheet resistance of the n-type layer at the LRL/n-type layer interface. The sheet resistance of the n-type layer is more than fifteen ohms per square.

In such a blue LED device, the LRL has two functions. A first function is that in the process of growing the n-type gallium-nitride layer, the presence of the LRL reduces the concentration of lattice defects in the n-type layer that otherwise would be present. The LRL functions to block dislocation threads originating in the lower template layer from extending up and into the n-type layer. A second function is a current spreading function. The LRL is formed such that a so-called two-dimensional gas of high mobility electrons is present in the layers of the superlattice of the LRL. As a result of this two-dimensional electron gas, the sheet resistance of the LRL at the LRL/n-type layer interface is substantially lower than the sheet resistance of the n-type layer. The relatively low resistivity LRL facilitates lateral current spreading on one side of the n-type layer. Current flow through the LRL/n-type layer interface plane during LED operation is therefore more uniform that it otherwise would be were the LRL not present.

In a second specific example, the original silicon wafer substrate, the buffer layer, the template layer, and the LRL are all removed. The LRL is entirely removed. Electrodes are added and the wafer bonded structure is singulated into individual LED devices. In each LED device, the n-type layer of the PAN structure is not in contact with any portion of the LRL because the LRL was completely removed. In this second specific example, the LRL serves the first function of reducing the concentration of lattice defects in the n-type layer.

In a second novel aspect, a wafer bonding process involves wafer bonding a carrier wafer structure to a device wafer structure by melting a layer of eutectic metal and thereby forming a wafer bonded structure. Prior to the melting, the device wafer structure involves an epitaxial LED structure disposed on a substrate, such as a silicon substrate upon which the epitaxial LED structure was grown. The device wafer structure further includes a layer of a non-reactive barrier metal disposed over the epitaxial LED structure. In one example, the layer of non-reactive barrier metal is a single layer of titanium that is more than 50 nm thick. In one example, the eutectic metal layer involves a first gold sublayer, a gold/tin sublayer, and a second gold sublayer, where the sold/tin sublayer is disposed between the two gold sublayers. When the eutectic metal layer melts, the non-reactive barrier metal layer prevents tin from the eutectic layer from diffusing through the non-reactive barrier layer. In one specific example, there is a highly reflective layer of silver disposed between the epitaxial LED structure and the non-reactive barrier metal layer. This silver layer provided a mirror function, and also serves as a electrical contact to the epitaxial LED structure. The non-reactive barrier metal layer prevents tin from the eutectic bonding metal layer from passing into this silver layer during the wafer bonding process. Were the tin allowed to diffuse into the silver mirror, then the reflectivity of the silver mirror might be decreased and the contact resistivity of the silver contact might be increased.

In a first advantageous aspect, a high temperature cycle that melts the eutectic metal layer involves heating the carrier wafer structure to a temperature of more than 280° C. (e.g., 310° C.), and maintaining this temperature for more than one minute. In a second advantageous aspect, there is at least one layer of platinum disposed between the epitaxial LED structure and the carrier of the carrier wafer structure, and the sum of all the thicknesses of all the layers of platinum between the epitaxial LED structure and the carrier is less than 200 nm. In a third advantageous aspect, there is one and only one layer of platinum between the epitaxial LED structure and the carrier. This platinum layer serves a silver-encapsulating function to prevent the electromigration of silver. The platinum encapsulation layer has a thickness of less than 200 nm. Wafer bonding results in a wafer bonded structure. After wafer bonding, the silicon substrate of the device wafer structure is removed, electrodes are added to the remaining wafer bonded structure, and the wafer bonded structure is singulated to form blue LED devices.

Platinum is a quite expensive metal, whereas titanium is substantially less expensive. The prior art wafer bonding process described above in the background section involves five or more platinum layers, each of which may be 100 nm or more in thickness. 500 nm or more of platinum is used in the prior art process. By reducing the amount of platinum used to a single layer that is thinner than 200 nm, the novel non-reactive metal bonding process disclosed here can reduce the cost of manufacturing blue LEDs on silicon substrates.

In a third novel aspect, a blue LED device is manufactured by epitaxially growing an n-type Gallium-Nitride (GaN) layer over a silicon substrate using Zinc-Sulfide (ZnS) as a transitional buffer layer. In one example, the ZnS buffer layer is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type GaN layer. First, the ZnS buffer layer provides a good lattice constant match with the silicon substrate and a compound polar template for subsequent GaN growth. Second, ZnS can be easily prepared by MOCVD such that all the epilayers are grown in one growth chamber. Third, the melting point of ZnS is 1850° C., which is high enough to keep it from becoming unstable during GaN deposition. Finally, if an aluminum-nitride (AlN) layer is also used as part of the buffer layer, then the ZnS layer is used as a diffusion barrier between the AlN layer and the silicon substrate. After the epitaxial layers of the epitaxial LED structure are formed, a carrier wafer structure is wafer bonded to the structure where the carrier wafer structure includes a conductive carrier. The original silicon substrate and the ZnS buffer layer are then removed from the wafer bonded structure. Electrodes are added and the wafer bonded structure is singulated to form finished LED devices.

In a fourth novel aspect, a vertical GaN-based blue LED device has an n-type layer that comprises multiple conductive intervening layers. In one example, the n-type layer contains a plurality of periods, and each period of the n-type layer includes a gallium-nitride (GaN) sublayer and an aluminum-gallium-nitride doped with silicon (AlGaN:Si) intervening sublayer. In one example, each GaN sublayer has a thickness of 900 nm, each AlGaN:Si intervening sublayer has a thickness less than 25 nm. Because AlGaN has a smaller lattice constant than GaN, the AlGaN:Si intervening layers provide a compressive strain to the GaN sublayers and prevent cracking. After each intervening layer, the quality of the overlying GaN sublayer is of improved quality in terms of lower density of lattice defects. In addition, the AlGaN:Si layers are electronically conductive (e.g., 1×10⁷ to 1×10⁹ defects per cm³) and have a silicon concentration greater than 1×10¹⁸ atoms/cm³. After the epitaxial layers of the epitaxial LED structure are formed, a carrier wafer structure is wafer bonded to the device wafer structure where the carrier wafer includes a conductive carrier. The original silicon substrate of the wafer bonded structure is then removed. Electrodes are added and the wafer bonded structure is singulated to form finished LED devices. Because the AlGaN:Si intervening sublayers are conductive (e.g., resistivity=1×10⁻²·Ω·cm), they do not need to be removed in the final LED device. Rather, the entire n-type layer remains in the completed blue LED device and has a thickness of at least two thousand nanometers to provide enhanced current spreading and to provide more n-GaN material to accommodate surface roughening.

Further details and embodiments and techniques are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, where like numerals indicate like components, illustrate embodiments of the invention.

FIG. 1 is a cross-sectional diagram of a white LED assembly in accordance with one novel aspect.

FIG. 2 is a top-down diagram of the white LED assembly of FIG. 1.

FIG. 3 is simplified and expanded cross-sectional diagram of the white LED assembly of FIG. 1.

FIG. 4 is a top-down diagram of the blue LED device of the white LED assembly of FIG. 1.

FIG. 5 is a cross-sectional diagram of a portion of the blue LED device of the white LED assembly of FIG. 1.

FIG. 6 is a cross-sectional diagram of the epitaxial PAN structure layers of the blue LED device of FIG. 3 formed on a silicon substrate.

FIG. 7 is a diagram that illustrates a step in a method of manufacturing where current blocking structures are added to the structure of FIG. 6.

FIG. 8 is a diagram that illustrates a step in the method of manufacturing where a highly reflective layer is added to the structure of FIG. 7.

FIG. 9 is a diagram that illustrates a step in the method of manufacturing where an encapsulation layer is formed over the structure of FIG. 8, and where a non-reactive barrier metal layer is formed over the encapsulation layer.

FIG. 10 is a diagram that illustrates a step in the method of manufacturing where bond metal is added to the structure of FIG. 9.

FIG. 11 is a diagram that illustrates a step in the method of manufacturing where a carrier wafer structure is wafer bonded to the structure of FIG. 10.

FIG. 12 is a graph that shows the temperature cycle of the thermal compressing wafer bonding process used.

FIG. 13 is a diagram that illustrates a step in the method of manufacturing where the wafer bonded structure is flipped.

FIG. 14 is a diagram that illustrates a step in the method of manufacturing where the silicon substrate, the buffer layer, and the template layer are removed from the structure of FIG. 12.

FIG. 15 is a top-down diagram of the wafer bonded structure after the removal step of FIG. 14 and after mesa have been formed.

FIG. 16 is a cross-sectional diagram of FIG. 15 taken along line B-B.

FIG. 17 is a diagram that illustrates a step in the method of manufacturing where the surface of the LRL is roughened.

FIG. 18 is a diagram that illustrates a step in the method of manufacturing where electrodes are added to the structure of FIG. 17.

FIGS. 19A and 19B together are a table that sets forth details about each of the steps in the method of manufacturing of FIGS. 6-18.

FIG. 20 is a cross-sectional diagram of a blue LED device 100 that is formed by the method of manufacture set forth above in connection with FIGS. 6-18, except that all LRL 4 is removed in the removal step illustrated in FIG. 14.

FIG. 21 is a cross-sectional diagram of a blue LED device 200 that is formed by the method of manufacture set forth above in connection with FIGS. 6-18, except that all LRL 4 is removed and some of the n-type layer 5 is removed in the removal step illustrated in FIG. 14.

FIG. 22 is a flowchart of a method in accordance with a first novel aspect.

FIG. 23 is a flowchart of a method in accordance with a second novel aspect.

FIG. 24 is a flowchart of a method in accordance with a third novel aspect.

FIG. 25 is a flowchart of a method in accordance with a fourth novel aspect.

DETAILED DESCRIPTION

Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings. In the description and claims below, when a first layer is referred to as being disposed “over” a second layer, it is to be understood that the first layer can be directly on the second layer, or an intervening layer or layers may be present between the first and second layers. The terms such as “over”, “under”, “upper”, “lower”, “top”, “bottom”, “upward”, “downward”, “vertically”, and “laterally” are used herein to describe relative orientations between different parts of the blue LED device being described, and it is to be understood that the overall blue LED device being described can actually be oriented in any way in three-dimensional space.

FIG. 1 is a cross-sectional side view of a white Light Emitting Diode (LED) assembly 50. FIG. 2 is a top-down diagram of the white LED assembly 50. The white LED assembly 50 includes four vertical blue LED devices 51-54. A vertical LED device is also sometimes referred to as a vertically-contacted LED device to distinguish it from a lateral or a laterally-contacted LED device. The four vertical blue LED devices 51-54 are mounted to a metal core Printed Circuit Board (PCB) 19. From the top-down perspective, the four vertical blue LED devices 51-54 are surrounded by a retaining ring 20. The retaining ring 20 retains an amount of phosphor 21 that covers the blue LED devices 51-54. A portion of a first metal structure 57 is exposed through a first opening in a soldermask layer 58. Anode electrodes of the blue LED devices 51-54 are surface mounted via amounts of silver epoxy 18 to the first metal structure 57 in this first opening. The first opening in the soldermask layer 58 also exposes a portion of a second metal structure 59. Upwardly facing cathode electrodes of the blue LED devices 51-54 are wirebonded to the exposed portion of the second metal structure 59. A first pad 60 is formed by another opening in soldermask layer 58. A second pad 61 is formed by yet another opening in soldermask layer 58. As illustrated in the cross-sectional view of FIG. 3, the first and second metal structures 57 and 59 are portions of a metal layer that is disposed on a dielectric layer 62. Dielectric layer 62 is a 35 um to 250 um thick layer of an epoxy material containing inorganic fillers like Al₂O₃. This dielectric layer 62 insulates the first and second metal structures 57 and 59 from an aluminum or copper base portion 63 of the metal core PCB 19.

FIG. 3 is a simplified cross-sectional side view of the white LED assembly 50. Only one vertical blue LED device 54 is illustrated in the diagram. The vertical blue LED device 54 includes numerous layers, some of which are illustrated in FIG. 3: a first metal electrode 17, a portion of a Low Resistance Layer (LRL)₄, an n-type gallium-nitride layer 5, an active layer 7, a p-type gallium-nitride layer 8, an amount of metal including a bond metal layer 13, a conductive carrier 15, and a second metal electrode 16. Reference numeral 64 identifies a wire bond that couples the first metal electrode 17 of the blue LED device 54 to the second metal structure 59. Metal 17 and LRL 4 are conductive and function to make electrical contact to the n-type layer 5. All the layers below p-type layer 8 (including layers 13, 15, 16) are conductive and function to make electrical contact to the p-type layer 8.

FIG. 4 is a top-down diagram of the vertical blue LED device 54. The first metal electrode 17 has a grid shape.

FIG. 5 is a more detailed cross-sectional diagram of the vertical blue LED device 54 taken along sectional line A-A in FIG. 3. Between the conductive carrier 15 and the p-type gallium-nitride 8 are multiple layers and structures including: a barrier metal layer 14, the bond metal layer 13, a barrier metal layer 12, a layer of an encapsulant metal 11, a highly reflective layer 10, and a current blocking layer 9. The current blocking layer 9 is patterned into current blocking structures. Between the active layer 7 and the n-type gallium-nitride layer 5 is a strain release layer 6. When current flows from the second electrode 16, through conductive carrier 15, through the metal layers 14, 13, 12, 11 and 10, through p-type gallium-nitride layer 8, through active layer 7, through strain release layer 6, through n-type gallium-nitride layer 5, through the Low Resistance Layer 4, and to the first electrode 17, then non-monochromatic and non-coherent light is emitted from the active layer 7. The emitted light has a wavelength in a range of from approximately 440 nm to approximately 490 nm. The term “non-monochromatic” as it is used here means that the light has a spectral line width that is substantially wider than the spectral line width of the light emitted by a typical laser diode. The spectral line width of an LED is typically around 20 nm wide, whereas the spectral line width of a laser diode is typically less than 4.0 nm wide.

FIGS. 6-18 is a set of diagrams that sets forth steps in a method of manufacturing the blue LED device 54. The diagrams are not to scale, but rather are conceptual diagrams.

FIG. 6 is a cross-sectional diagram that shows the result of several initial steps of forming epitaxial layers on a silicon substrate 1. Silicon substrate 1 is a monocrystalline silicon substrate wafer of the type commonly used in the manufacture of high volume CMOS integrated circuits. A buffer layer 2 is formed on the silicon substrate. In the illustrated example, the forming of this buffer layer 2 involves first forming a less than 100 nm thick layer 65 of zinc-sulfide (for example, 50 nm) on silicon substrate 1. A 200 nm thick layer 66 of aluminum-nitride (AlN) is then formed on the ZnS layer 65. A 250 nm thick layer 67 of aluminum-gallium-nitride (AlGaN) is then formed on the AlN layer 66. Although this particular buffer layer involving a layer of zinc-sulfide is shown, other types of buffer layers can be used. A buffer layer of a single layer of AlN may, for example, be used. Where the ZnS layer 65 is provided, the AlN layer 66 and the AlGaN layer 67 illustrated in FIG. 6 are optional.

The manufacturing of vertical LED device 54 involves epitaxially later growing a Gallium-Nitride (GaN) layer (e.g., n-type GaN layer 5) over silicon substrate 1. The in-plane lattice constants of GaN and Si are aGaN(0001)=3.189 Å, and aSi(111)=3.840 Å, respectively. As a result, there is a substantial 20.4% in-plane lattice mismatch between GaN and Si. This lattice mismatch, combined with a large difference in the thermal expansion coefficient between GaN and Si (e.g., 56%), makes growing high quality, thick, and crack-free GaN on silicon substrate a challenge. In general, using a transitional buffer layer satisfying coincident lattice conditions can alleviate the lattice mismatch. For example, an AlN layer 66 (aAlN=3.112 Å) is often used as a buffer layer to provide a compression to a GaN epilayer. However, inter diffusion of Al and Si at the interface is severe, resulting in high unintentional doping levels. Moreover, AlN crystal quality is low because the lattice mismatch between AlN and Si is even higher than the lattice mismatch between GaN and Si.

To overcome this drawback, ZnS layer 65 is used as a new transitional buffer layer. First, Wurzite ZnS compound (aZnS=3.811 Å) has a lattice constant of 0.3811, which is between the lattice constant of GaN and Si, and is closer to the lattice constant of Si. ZnS thus provides a good lattice constant match with Si and is also a compound material like GaN. Second, ZnS can be easily prepared by metalorganic chemical vapor deposition (MOCVD) such that all the epilayers are grown in one growth chamber. MOCVD is a chemical vapor deposition method of epitaxial growth of materials, especially compound semiconductors from the surface reaction of organic compounds or metalorganics and metal hydrides containing the required chemicals. In one example, ZnS is grown on a silicon substrate in an MOSCVD chamber by introducing hydrogen sulfide with dimethyl zinc (DMZn), under 350° C. growth temperature and 100 Torr growth pressure. Third, the melting point of ZnS is 1850° C., which is high enough to keep it from becoming unstable during GaN deposition. Finally, if an AlN layer is also used as part of the buffer layer, then ZnS also serves as a diffusion barrier between AlN of the buffer and the silicon substrate.

A template layer 3 is then formed on the buffer layer 2. In the illustrated example, template layer 3 is a 1000 nm thick layer of undoped gallium-nitride.

Rather than growing the n-type layer of the LED directly on the template layer, the Low Resistance Layer (LRL) 4 is grown directly on the template layer 3. In the illustrated example, LRL 4 is a superlattice structure that is structured so that a two-dimensional gas of high mobility electrons is formed in its layers. The superlattice structure includes multiple periods, where each period is less than 300 nm thick. In one specific example, each period includes a 100 nm thick n-type gallium-nitride sublayer and a 25 nm thick undoped aluminum-gallium-nitride sublayer. In the perspective of the illustration of FIG. 6, a 100 nm thick n-GaN sublayer is disposed directly on template layer 3. Also, the uppermost sublayer of the LRL 4 is a 100 nm thick n-GaN sublayer. There are five GaN sublayers, and four AlGaN sublayers in the configuration illustrated. The n-GaN layers are doped with silicon to a concentration of 1×10¹⁸ atoms/cm³. Each of the thinner AlGaN sublayers is strained to the lattice of a thicker GaN sublayer or sublayers.

The n-type GaN layer 5 is then grown on LRL 4. It is difficult to grow a thick layer of high quality GaN that has a low lattice defect density and that does not suffer from cracking and other problems due to the buildup of stresses in the GaN layer. For example, there exists a large difference in thermal expansion coefficient (e.g., 56%) between GaN and Si. This thermal mismatch usually causes tensile stress in the GaN epilayer during cool down. When the thickness of the GaN epilayer is larger than 1000 nm, cracks usually occur. Although the exact reasons for the buildup of stress as a GaN layer grows thicker are not fully understood, it is empirically known that cracking may be prevented by stopping the growth of the GaN layer just before the buildup of stress in the GaN layer would result in cracking. At this point, a thin intervening layer is grown on the top of the GaN layer. This intervening layer may, for example, be a 5 nm thick layer of AlN. After the formation of the thin intervening sublayer, another sublayer of GaN is grown on the intervening layer. This second GaN sublayer is grown to be as thick as possible without the GaN sublayer having too much internal stress. This periodicity is repeated multiple times. After each intervening layer, the quality of the overlying GaN sublayer is of improved quality in terms of lower density of lattice defects. For example, typical GaN over Si has a defect density as high as 1×10¹° defects per cm³. The defect density of improved quality GaN over Si is in the range from 1×10⁷ to 1×10⁹ defects per cm³.

The use of AlN intervening sublayers, however, leads to one problem. AlN is an insulating material due to its wide bandgap (e.g., 6.2 eV) and therefore creates a barrier for current transportation in vertical direction. As a result, all the sublayers from the silicon substrate to the top AlN intervening sublayer have to be removed if a vertical LED is to be made. The current spreading function of these layer is therefore not to bear in the final LED device. The GaN sublayer over the top AlN sublayer is usually less than 2000 nm, which could cause a current crowding problem in LED devices. To solve this problem, a thin AlGaN:Si layer is used as a new intervening sublayer instead of using AlN. First, AlGaN:Si is an n-type material which allows electron transportation through it because AlGaN has smaller band energy (e.g., bandgap of 3.4 eV to 6.2 eV, depending on the Al concentration) than that of AlN, thus the activation energy of Si in AlGaN is smaller than that of Si in AlN. As a result, the AlGaN:Si intervening sublayers are electronically conductive and do not need to be removed in the final LED device. One example of the resistivity of the conductive AlGaN:Si layer is 1×10⁻²·Ω·cm. Second, AlGaN has a smaller lattice constant than GaN and therefore provides a compressive strain to the subsequent GaN sublayers and helps prevent cracking.

In the example of FIG. 6, each of the GaN sublayers of n-type GaN layer 5 has a thickness of about 900 nm and is doped with silicon at a concentration of 5×10²⁸ atoms/cm³. Each of the intervening sublayers sublayer of AlGaN:Si less than 25 nm in thickness (for example, 5 nm) with a silicon dopant concentration of 1×10¹⁸ atoms/cm³. These AlGaN:Si intervening sublayers are relatively conductive, and the n-type GaN intervening sublayers are conductive, so the overall n-type GaN layer 5 can effectively conduct current in the direction from the LRL/n-type layer interface toward the active layer. The bottom sublayer of n-type GaN layer 5 that is in direct contact with LRL 4 is a 900 nm thick GaN sublayer as illustrated. The upper sublayer of the n-type gallium-nitride layer 5 is also a 900 nm sublayer of GaN as illustrated. The entire n-type GaN layer 5 with multiple AlGaN:Si conductive intervening sublayers is approximately 5000 nm thick, where each n-GaN sublayer is substantially thicker than the n-GaN sublayers of LRL 4.

There is an interface 74 between the n-type GaN layer 5 and the underlying LRL 4. The n-type GaN layer 5 has a sheet resistance at this interface that is greater than 15 ohms per square. The LRL 4 also has a sheet resistance at this interface, but the sheet resistance of LRL 4 is lower than the sheet resistance of the n-type GaN layer 5. In one example, the sheet resistance of LRL 4 can be destructively measured by grinding away the upper layers of a first LED device to expose a surface of LRL 4 at interface 74, and then probing the exposed LRL surface and measuring its sheet resistance. In a similar fashion, the sheet resistance of n-type layer 5 can be destructively measured by grinding away the lower layers of a second LED device to expose a surface of n-type layer 5 at interface 74, and then probing the exposed n-type layer surface and measuring its sheet resistance.

Next, a strain release layer 6 is formed on the n-type GaN layer 5. In one example, strain release layer 5 is 120 nm thick and includes thirty periods. Each period includes a first sublayer of In_(x)Ga_(1-x)N, where 0<x<0.12 and a second sublayer of In_(y)Ga_(1-y)N where 0<y<0.12.

Next, the active layer 7 is formed on the strain release layer 6. The active layer 7 is fashioned to emit blue light in the overall blue LED device. In one example, active layer 7 is a 130 nm thick Multiple Quantum Well (MQW) structure that has ten periods. Each period includes a 3 nm thick InGaN sublayer (15% In), and a 10 nm thick GaN sublayer. The active layer 7 emits non-monochromatic light having a wavelength in the range of approximately 440 nm to approximately 490 nm.

Next, the p-type GaN layer 8 is formed on the active layer 7. In one example, the p-type GaN layer is 300 nm thick and has a magnesium dopant concentration of 1×10²° atoms/cm³. In this example, the upper surface of p-type GaN layer 8 is formed so that the completed LED device will emit non-monochromatic light and will include no current focusing ridge structures of the type used in laser diodes. The n-type layer 5, the p-type layer 8, and all layers in between including active layer 7 together are an epitaxial LED structure 80.

FIG. 7 is a cross-sectional diagram that shows a subsequent step in the method of manufacture. A current blocking layer of an insulating material is formed on the upper surface of the p-type GaN layer 8. In one example, the current blocking layer is a patterned 200 nm thick layer of silicon dioxide. This silicon dioxide layer is deposited and patterned using photolithographic techniques to form structures that obstruct current flow in some places more than in other places. For example, the large structure 66 of the current blocking layer is disposed directly under the location where the first electrode 17 will be formed later in the manufacturing method. The large structure 66 is placed in this location so that current will not flow through the active layer directly underneath the first electrode 17, and therefore will not generate light directly under the first electrode 17. Had light been generated in the active region directly underneath the first electrode, then a large amount of that light might be blocked by the metal first electrode 17 from escaping the LED device. The blocked light might be reabsorbed in the LED without ever escaping the LED as usable light. The current used to generate that blocked light would therefore be wasted. By blocking current from flowing through the portion of the active layer directly under the first electrode 17, this current is made to flow through the active layer in other places where the resulting light has a better chance of escaping the LED device as useful light. By blocking an appropriate proportion of each sub-area of the upper surface area of the p-type layer 8, and by properly varying this proportion across from sub-area to sub-area across the upper surface area of the p-type layer 8, the amount of current flowing through each individual sub-area is controlled to maximize light output from the LED device as compared to current flow through the overall LED device.

FIG. 8 is a cross-sectional diagram that shows a subsequent step in the method of manufacture. A highly reflective layer 10 is deposited over the current blocking layer 9. In one example, highly reflective layer 10 is a 200 nm thick layer of silver that makes ohmic contact to the p-type GaN layer 8. This silver layer does not cover the entire LED device wafer. The highly reflective layer 10 is shown covering the entire structure of FIG. 8 because the cross-section of FIG. 8 is a cross-section of only a part of the LED device along line A-A. Highly reflective layer 10 serves a first function of acting as a mirror to reflect light and serves a second function of making electrical contact to the p-type layer 8.

FIG. 9 is a cross-sectional diagram that shows a subsequent step in the method of manufacture. An encapsulation layer 11 covers the silver layer 10. In the illustrated example, encapsulation layer 11 is a 100 nm thick layer of platinum. This layer of platinum blocks the electromigration of silver. In one advantageous aspect, this layer of platinum is the only layer of platinum in the blue LED device. The sum of all the thicknesses of all platinum layers of the blue LED device (there is only one layer of platinum) is less than 200 nm.

After encapsulation layer 11 is formed, a non-reactive barrier metal layer 12 more than 50 nm thick is formed over the encapsulation layer. In the illustrated example, the non-reactive barrier metal layer 12 is a 200 nm thick layer of titanium. The titanium is a barrier in that it is a barrier to the diffusion of tin. Tin, from a bond metal layer to be later applied to the top of the structure, is blocked by the barrier layer from diffusing into the silver of layer 10. Some other metals such as platinum, titanium/tungsten, gold and nickel that are sometimes used as barriers for tin, are actually somewhat reactive with tin. In other bonding processes that use such reactive metals as barriers, the combination of the thickness of the reactive metal provided and the limited time of the high temperature bonding cycle is such that the amount of tin incursion is kept within acceptable levels. The non-reactive barrier metal of layer 12, in contrast, is not such a reactive metal and in one example is a layer of titanium that is more than 50 nm thick.

FIG. 10 is a cross-sectional diagram that shows a subsequent step in the method of manufacture. A 500 nm thick sublayer of gold is formed to cover the top of non-reactive barrier metal layer 12. Reference numeral 13 in FIG. 10 denotes this gold sublayer that is one sublayer of three-sublayer Au/AuSn/Au sandwich structure of metal layers.

FIG. 11 is a cross-sectional diagram that shows a subsequent step in the method of manufacture. The conductive carrier 5 is covered with an adhesion and barrier metal layer 14. In the illustrated example, the conductive carrier is a monocrystalline silicon wafer and the adhesion and barrier metal layer 14 is a 200 nm thick layer of titanium. Gold does not generally bond well to silicon, but titanium does, so the titanium layer 14 is provided to bond to the conductive silicon carrier 15 so that a subsequent sublayer of gold (part of the bond metal layer 13) can then in turn bond to the titanium. In addition to this adhesion function, the titanium also acts as a barrier to prevent tin and gold from diffusing to the silicon surface and degrading the adhesion. In another example, the adhesion/barrier metal layer 14 also includes a layer of platinum disposed over the titanium.

A 500 nm thick sublayer of gold is then formed on the adhesion and barrier metal layer 14, and a 3000 nm thick gold/tin sublayer is formed on the gold sublayer. The 3000 nm thick gold/tin sublayer is 80 percent gold and 20 percent tin by weight. These gold and gold/tin sublayers are the other two sublayers of the three-sublayer sandwich metal structure 13 mentioned above in connection with FIG. 9.

The conductive carrier 15, the barrier metal layer 14, and the gold and gold/tin sublayers 13 together are a carrier wafer structure 68. The silicon substrate 1 and the layers formed on it together are a device wafer structure 69. The carrier wafer structure 68 is wafer bonded to the gold covered upper surface of the device wafer structure 69.

FIG. 12 is a graph showing the temperature cycle of the thermal compression wafer bonding process used. Carrier wafer structure 68 is pressed against device wafer structure 69 with a pressure of approximately fifty pounds per square inch and the pressed together wafers are heated to at least 280° C. In the specific example, the wafers are heated to 310° C. The wafers remain at this elevated temperature for a period of more than one minute to ensure there is a uniform melting temperature all across the wafers. In the specific example, the elevated temperature is maintained for five minutes. The eutectic gold/tin sublayer melts, thereby wafer bonding the carrier wafer structure 68 to the device wafer structure 69. This wafer bonding is represented by arrows 70 in FIG. 11. At a twenty percent tin concentration, the gold/tin sublayer has a melting point of approximately 282° C. Once the gold/tin sublayer melts, however, some of the tin diffuses from this sublayer into the gold sublayers on either side of the gold/tin sublayer. The concentration of tin in the gold/tin sublayer therefor decreases. A gold/tin layer having a lower concentration of tin has a higher melting temperature. For every one percent that the tin concentration decreases in the gold/tin alloy, the melting temperature of the gold/tin alloy increases by approximately 30° C. Accordingly, after the wafer bonding process has been conducted, the concentration of tin in the gold/tin sublayer decreases to be below twenty percent and the overall wafer bonded structure can thereafter have its temperature raised to 282° C. without the gold/tin sublayer melting.

FIG. 13 shows a subsequent step in the method of manufacture. The resulting wafer bonded structure 71 is flipped as indicated by arrow 72.

FIG. 14 shows a subsequent step in the method of manufacture. The silicon substrate 1, the buffer layer 2 and the template layer 3 are removed from wafer bonded structure 71 as indicated by arrow 73. In the present example, these layers are removed using Chemical Mechanical Polishing (CMP) and reactive ion etching (RIE) techniques such that one of the GaN sublayers of LRL 4 is present and exposed at the top of the structure. The entire n-type GaN layer 5 is left as part of the wafer bonded structure 71. Due to the conductivity of the AlGaN:Si intervening sublayers within layer 5, the n-type GaN layer 5 is electrically conductive from the strain release layer to n-type layer interface, all the way through the n-type GaN layer, and to the n-type layer/LRL interface. An advantage of using AlGaN:Si for the intervening sublayers as opposed to using AlN intervening sublayers is that the AlGaN:Si intervening sublayers are conductive. There is no nonconductive intervening AlN sublayer within the n-type GaN layer that must be removed in the step of FIG. 13 in order to provide conductivity through the n-type layer. Rather, the entire n-type GaN layer 5 remains in the completed blue LED device.

FIG. 15 is a top-down diagram of the wafer bonded structure 71. In addition to removing the layers 1, 2 and 3 as illustrated in FIG. 14, wet etching is used to etch horizontal and vertical streets down to the encapsulation layer 11, thereby forming a two-dimensional array of rows and columns of mesa structures. Reference numerals 75, 76 and 77 identify three such streets. Reference numerals 78 and 79 identify two of the mesa structures.

FIG. 16 is a cross-sectional diagram of the structure of FIG. 15 taken along sectional line B-B. The non-reactive barrier layer 12 of titanium is shown in cross-hatching. Non-reactive barrier layer 12 is a single layer of titanium more than 50 nm thick and includes no sublayers, no platinum, and no tungsten. Silver of the highly reflective layer 10 is blocked by the encapsulation layer 11 from moving laterally out from under the mesas. The silver of the highly reflective layer 10 is contained from the top by the bottom surface of the p-type GaN layer 8 (the bottom of the mesas).

FIG. 17 shows a subsequent step in the method of manufacture. The upper surface of the exposed LRL 4 at the top of each mesa is roughened. This roughening is the type of roughening customarily performed to facilitate the escape of light form the LED device. The roughening is actually more severe than is illustrated in FIG. 17. The vertical distance from the highest peak to the deepest valley of the roughened surface is approximately 500 nm, so the deepest valleys extend down into the n-type layer 5. It is desirable that the LRL not be penetrated, so in another example the amount material removed is preferably limited to removing the silicon substrate and part of the buffer layer.

FIG. 18 shows a subsequent step in the method of manufacture. The second electrode 16 is formed on the conductive carrier 15 as illustrated. In one example, second electrode 16 includes a first 20 nm thick nickel sublayer that is in direct contact with the conductive carrier 15, and also includes a second 200 nm thick gold layer that covers the nickel sublayer. Second electrode 16 is therefore 220 nm thick.

In addition, FIG. 18 shows a subsequent step of forming the first electrode 17 on the upper surface of LRL 4 as illustrated. In one example, first electrode 17 includes a 20 nm thick sublayer of titanium disposed directly on LRL 4, a 100 nm thick sublayer of aluminum disposed on the titanium sublayer, a 20 nm thick sublayer of nickel disposed on the aluminum sublayer, and a 200 nm thick sublayer of gold disposed on the nickel sublayer. First electrode 17 is therefore approximately 340 nm thick. The dopant concentration in the GaN sublayers of LRL 4 is adequately high that good ohmic contact is formed between metal 17 and LRL 4.

After the first and second electrodes have been added as shown in FIG. 18, the wafer bonded structure is singulated into separate blue LED devices. Singulation is performed by sawing the wafer bonded structure down the streets illustrated in FIG. 15 so that each mesa structure becomes a separate blue LED device. In the illustrated example, one of the resulting blue LED devices is then incorporated into the white LED assembly of FIGS. 1-3. The second electrode 16 is glued down to the metal core PCB 19 as illustrated in FIG. 3 using a layer of silver epoxy 18. The first metal electrode 17 is wirebonded via bond wire 64 to the second metal structure 59 of metal core PCB 19 as illustrated. After wirebonding, the retaining ring 20 of silicone is formed on the structure by silk screening. Alternatively, the retaining ring 20 is cut and shaped to the right dimensions, and then applied. Ring 20 is 0.5 to 3.0 mm high, and 0.2 mm to 1.5 mm wide. After the silicone has cured, the amount of phosphor 21 is dropped onto the blue LED device 54 so that it is retained by ring 20. The phosphor 21 is allowed to cure to form the completed white LED assembly 50.

FIG. 19 is a table that sets forth details about each step of the method of manufacture. The numbers in the left column of the table are the reference numerals for the various layers of the white LED assembly 50.

FIG. 20 is a cross-sectional diagram of a blue LED device 100 that is formed by the method of manufacture set forth above in connection with FIGS. 6-18, except that all LRL 4 is removed in the removal step illustrated in FIG. 13. All or substantially all of the n-type layer 5 remains in the finished blue LED device 100. FIG. 17 is not to scale, but rather is a conceptual diagram.

FIG. 21 is a cross-sectional diagram of a blue LED device 200 that is formed by the method of manufacture set forth above in connection with FIGS. 6-18, except that all LRL 4 is removed and some of the n-type layer 5 is removed in the removal step illustrated in FIG. 13. All of the thin intervening sublayers of the n-type layer are removed, leaving only the last 900 nm thick GaN sublayer. This last GaN sublayer remains in the finished blue LED device 200. FIG. 18 is not to scale, but rather is a conceptual diagram.

FIG. 22 is a flowchart of a method 300 in accordance with a first novel aspect. A superlattice structure is formed (step 301) over a silicon substrate. The superlattice structure includes a plurality of periods. Each period is less than 300 nm thick and includes a GaN sublayer. In one example, a buffer layer is formed on the silicon substrate, and a template layer is formed on the buffer layer, and the superlattice structure is formed on the template layer. Next, an n-type GaN layer is formed (step 302) directly on the superlattice structure. An active layer containing indium is formed (step 303) over the n-type layer. A p-type GaN layer is formed (step 304) over the active layer. The silicon substrate, the superlattice structure, the n-type layer, the active layer, and the p-type layer together are a first structure. A conductive carrier is bonded (step 305) to the first structure thereby forming a second structure. The silicon substrate is then removed (step 306) from the second structure thereby forming a third structure. Electrodes are formed (step 307) on the third structure. The third structure is then singulated (step 308) thereby forming a blue LED device.

Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. LRL 4 can be fabricated in numerous different suitable ways. In one example, LRL 4 involves periods, where each period includes a first aluminum-gallium-nitride layer and a second aluminum-gallium-nitride layer, where the aluminum concentrations in the two sublayers differ from one another. The composition of the two sublayers is given by Al_(x)Ga_(1-x)N/Al_(y)Ga_(1-y)N, where x and y are different nonzero numbers. Although a specific example is described above in which the aluminum-gallium-nitride and gallium-nitride sublayers of the LRL are of different thicknesses, in other examples the sublayers are of substantially the same thickness. In an AlGaN/GaN or AlGaN/AlGaN superlattice the aluminum concentration in one sublayer containing aluminum can be graded. The LRL can be an AlInN/GaN superlattice. The LRL can be an AlGaN/AlGaN/GaN superlattice where each period involves three sublayers.

Although the wafer bonding process involving a non-reactive barrier metal layer is described above in connection with an LED device that after wafer bonding is glued using silver epoxy to a metal core PCB to form the completed white LED assembly, the wafer bonding process is usable where an LED is provided with a gold/tin layer for die attachment. Due to the decreased concentration of tin in the gold/tin sublayer of metal bonding layer 13 during wafer bonding, the melting temperature of the metal bonding layer 13 is higher than 280° C. after the wafer bonding process has been performed. Accordingly, a completed LED device can be heated to a high enough temperature to melt an amount of gold/tin provided for die attachment purposes without melting the metal bonding layer 13 within the LED device itself. Although the wafer bonding process is described above in connection with an example in which the eutectic layer is a gold/tin layer, the wafer bonding process is not limited to require a gold/tin eutectic layer. In other examples the eutectic layer is a type of metal layer such as, for example, a gold/indium metal layer, and a palladium/indium metal layer. Although the wafer bonding process is described above in connection with an example where the silver encapsulation layer is platinum, other encapsulation layers such as nickel and rhodium may be employed.

FIG. 23 is a flowchart of a method 400 in accordance with a second novel aspect. An epitaxial LED structure is grown (step 401) on a non-GaN substrate. The non-GaN substrate in one example is a silicon substrate and appropriate intervening buffer and template layers are employed. A silver layer is then provided (step 402) over the epitaxial LED structure to function as a mirror and to function as an ohmic contact to the epitaxial LED structure. An encapsulating layer is provided (step 403) over the silver layer. In one example, the encapsulating layer is a single layer of platinum that is less than 200 nm thick. A layer of non-reactive barrier metal is provided (step 404) over the encapsulating layer, thereby forming a device wafer structure. In one example, this non-reactive barrier metal layer is a single layer of titanium that is more than 50 nm thick. This single layer of titanium layer includes substantially no tungsten.

A carrier wafer structure includes a conductive carrier. The conductive carrier may be conductive silicon wafer. The carrier wafer structure is then wafer bonded (step 405) to the device wafer structure by melting a eutectic metal layer between the two wafer structures, thereby forming a wafer bonded structure. In one example, the eutectic metal layer involves a gold/tin sublayer having a melting temperature of approximately 282° C. This eutectic metal layer is melted by raising the temperature of the carrier wafer structure to more than 280° C. (for example, to 310° C.) and maintaining this elevated temperature for more than one minute.

In one example, the temperature of the carrier wafer structure is indirectly determined by placing an amount of gold/tin of the same composition of the eutectic bond metal layer in a fully loaded furnace chamber, and slowly increasing the set point of the furnace chamber until the gold/tin is observed to melt. This set point is assumed to correspond to a carrier device wafer temperature of 282° C. The set point of the furnace chamber is then increased an additional amount that is known to correspond to an increased furnace chamber temperature of 30° C. The wafer bonding process is carried out by using this increased furnace chamber setting for at least one minute without actually directly measuring the temperature of the wafer bonded structure within the furnace chamber.

After wafer bonding, the non-GaN substrate of the resulting wafer bonded structure is the removed (step 406). Electrodes are formed on the wafer bonded structure (step 407) and the wafer bonded structure is singulated thereby forming a plurality of blue LED devices (step 408). In one example of the method 400, the total thickness of any and all platinum layers in the completed blue LED devices is less than 200 nm and the high temperature bond metal melting cycle (when the temperature of the carrier wafer structure is greater than 280° C.) is more than one minute.

FIG. 24 is a flowchart of a method of manufacturing an LED device on silicon substrate using Zinc-Sulfide (ZnS) as a buffer layer in accordance with a third novel aspect. A Zinc-Sulfide (ZnS) layer is formed (step 501) over and directly on a silicon substrate. In one embodiment, the ZnS layer is a buffer layer formed on the silicon substrate and a template layer is then formed on the buffer layer. Optionally, an aluminum-nitride (AlN) layer is formed over the zinc-sulfide layer, and an aluminum-gallium-nitride (AlGaN) layer is formed over the aluminum-nitride layer. The ZnS layer, the AlN layer, and the AlGaN layer form the buffer layer. Next, an n-type GaN layer is formed (step 502) over the template layer. An active layer containing indium is formed (step 503) over the n-type layer. A p-type GaN layer is formed (step 504) over the active layer. The n-type layer, the active layer, and the p-type layer together are an epitaxial LED structure. The silicon substrate, the ZnS layer, the epitaxial LED structure together are a first structure. In one example, the first structure is device wafer structure 69 of FIG. 11. A conductive carrier is then bonded (step 505) to the first structure thereby forming a second structure. In one example, the carrier is part of a carrier wafer structure such as carrier wafer structure 68 of FIG. 11. The original silicon substrate and the ZnS layer are then removed (step 506) from the second structure thereby forming a third structure. Electrodes are formed (step 507) on the third structure. The third structure is then singulated (step 508) thereby forming a blue LED device.

FIG. 25 is a flowchart of a method of manufacturing a blue LED device on silicon substrate in accordance with a fourth novel aspect. The blue LED device has an n-type gallium-nitride layer with multiple conductive intervening sublayers. An n-type layer is formed (step 601) over a silicon substrate. The n-type layer comprises a plurality of periods, each period of the n-type layer includes a gallium-nitride (GaN) sublayer and an aluminum-gallium-nitride doped with silicon (AlGaN:Si) intervening sublayer. The AlGaN:Si intervening sublayers are doped with Si and are electronically conductive. Next, an active layer containing indium is formed (step 602) over the n-type layer. A p-type GaN layer is formed (step 603) over the active layer. The silicon substrate, the n-type layer, the active layer, and the p-type layer together form a first structure. A conductive carrier is bonded (step 604) to the first structure thereby forming a second structure. The silicon substrate is then removed (step 605) from the second structure thereby forming a third structure. Electrodes are formed (step 606) on the third structure. The third structure is then singulated (step 607) thereby forming a blue LED device.

Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims. 

1. A method of manufacturing a Light Emitting Diode (LED) device, comprising: (a) forming a superlattice structure over a silicon substrate, wherein the superlattice structure includes a plurality of periods, and wherein each period of the superlattice structure includes an aluminum-gallium-nitride sublayer and a gallium-nitride sublayer; (b) forming an n-type layer over and directly on the superlattice structure; (c) forming an active layer over the n-type layer, wherein the active layer includes an amount of indium; (d) forming a p-type layer over the active layer such that the silicon substrate, superlattice structure, the n-type layer, the active layer, and the p-type layer form a first structure; (e) bonding a conductive carrier to the first structure thereby forming a second structure; and (f) removing the silicon substrate from the second structure thereby forming a third structure.
 2. The method of manufacturing of claim 1, further comprising: (g) forming electrodes on the third structure; and (h) singulating the third structure thereby forming the LED device.
 3. The method of manufacturing of claim 1, wherein the n-type layer comprises a plurality of periods, wherein each period of the n-type layer includes a gallium-nitride sublayer and an aluminum-gallium-nitride, wherein gallium-nitride sublayers of the n-type layer are thicker than the gallium-nitride sublayers of the superlattice, and wherein the aluminum-gallium-nitride sublayers of the n-type layer are thinner than the aluminum-gallium-nitride sublayers of the superlattice.
 4. The method of manufacturing of claim 1, wherein the aluminum-gallium-nitride sublayers of the superlattice have a silicon concentration less than 1×10¹⁸ atoms/cm³, and wherein the aluminum-gallium-nitride sublayers of the n-type layer have a silicon concentration greater than 1×10¹⁸ atoms/cm³.
 5. The method of manufacturing of claim 1, wherein the superlattice structure meets the n-type layer at an interface, wherein the superlattice structure has a sheet resistance at the interface, wherein the n-type layer has a sheet resistance at the interface, and wherein the sheet resistance of the superlattice structure at the interface is smaller than the sheet resistance of the n-type layer at the interface.
 6. The method of manufacturing of claim 1, wherein the n-type layer comprises a plurality of periods, wherein each period of the n-type layer includes a relatively thick sublayer of gallium-nitride and a relatively thin layer of another material, and wherein the other material is taken from the group consisting of: aluminum nitride, and silicon doped aluminum-gallium-nitride.
 7. The method of manufacturing of claim 2, wherein the superlattice structure is entirely removed along with the silicon substrate in (f).
 8. The method of manufacturing of claim 2, wherein some but not all of the superlattice structure is removed along with the silicon substrate in (f).
 9. The method of manufacturing of claim 2, wherein the superlattice structure and a part of the n-type layer are removed along with the silicon substrate in (f).
 10. The method of manufacturing of claim 1, further comprising: (g) before (a) forming a buffer layer on the silicon substrate, and then forming a template layer on the buffer layer, wherein the superlattice structure is formed directly on the template layer in (a).
 11. The method of manufacturing of claim 1, further comprising: after (f) roughening a surface of the superlattice structure.
 12. The method of claim 1, wherein the bonding of (e) involves using a eutectic bond metal layer to wafer bond a carrier wafer structure to the first structure, wherein the conductive carrier is a part of the carrier wafer structure.
 13. A Light Emitting Diode (LED) device for emitting non-monochromatic light, the LED device comprising: a Low Resistance Layer (LRL) that includes a plurality of periods, wherein at least one of the periods of the LRL includes an aluminum-gallium-nitride sublayer and a gallium-nitride sublayer; an n-type layer disposed in direct contact with the LRL; a p-type layer; an active layer disposed between the n-type layer and the p-type layer, wherein the active layer includes an amount of indium; a conductive carrier; a first electrode; and a second electrode adapted to conduct a current, wherein the current flows from the second electrode, through the conductive carrier, through the p-type layer, through the active layer, through the n-type layer, through the LRL, and to the first electrode thereby causing the non-monochromatic light to be emitted.
 14. The LED device of claim 13, wherein the n-type layer comprises a plurality of periods, wherein each period of the n-type layer includes a gallium-nitride sublayer and an aluminum-gallium-nitride, wherein gallium-nitride sublayers of the n-type layer are thicker than the gallium-nitride sublayers of the LRL, and wherein the aluminum-gallium-nitride sublayers of the n-type layer are thinner than the aluminum-gallium-nitride sublayers of the LRL.
 15. The LED device of claim 14, wherein the aluminum-gallium-nitride sublayers of the LRL have a silicon concentration less than 1×10¹⁸ atoms/cm³, and wherein the aluminum-gallium-nitride sublayers of the n-type layer have a silicon concentration greater than 1×10¹⁸ atoms/cm³.
 16. The LED device of claim 15, wherein the LRL has a sheet resistance, wherein the n-type layer has a sheet resistance, and wherein the sheet resistance of the LRL is smaller than the sheet resistance of the n-type layer.
 17. The LED device of claim 13, wherein the LRL has a roughened surface, and wherein the first electrode is in direct contact with the LRL.
 18. The LED device of claim 13, further comprising: a eutectic bond metal layer disposed between the conductive carrier and the p-type layer.
 19. A method of manufacturing, comprising: (a) bonding a conductive carrier to a first structure thereby forming a second structure, wherein the first structure involves: a silicon substrate; a superlattice structure disposed on the silicon substrate, wherein the superlattice structure includes a plurality of periods, wherein each period is less than three hundred nanometers thick and includes a sublayer of gallium nitride; an n-type gallium-nitride layer disposed directly on the superlattice structure; a p-type gallium-nitride layer; and an active layer disposed between the n-type gallium-nitride layer and the p-type gallium-nitride layer, wherein the active layer comprises an amount of indium.
 20. The method of manufacturing of claim 19, further comprising: (b) removing the silicon substrate from the second structure thereby forming a third structure; and (c) forming metal electrodes on the third structure.
 21. The method of manufacturing of claim 19, further comprising: (b) removing the silicon substrate and some but not all of the superlattice structure from the second structure thereby forming a third structure that includes a part of the superlattice structure; and (c) forming metal electrodes on the third structure.
 22. The method of manufacturing of claim 19, further comprising: (b) removing the silicon substrate and all of the superlattice structure from the second structure thereby forming a third structure; and (c) forming metal electrodes on the third structure.
 23. The method of manufacturing of claim 19, further comprising: (b) removing the silicon substrate, all of the superlattice structure, and some but not all of the n-type gallium-nitride layer from the second structure thereby forming a third structure that includes a part of the n-type layer; and (c) forming metal electrodes on the third structure. 